Below are details of the Shamroc DAC testing board.
- Daughterboard, for DAC 1 (DAC not present yet)
- Daughterboard, for DAC 2 (daughterboard not present yet)
- Filtering, plus the high-accuracy ADC is here as well (which measures back whatever the DACs set)
- Reference power
- Controlling of heaters
- Two housekeeping ADCs, with lower accuracy than the one that's located at 3
- Power for DACs and filtering
- Power supplies
- Additional input for power
- Barrier
- Additional clock input for DACs
- Connection from FPGA
- Connection from FPGA for the DAC clock signal (40 MHz)
- Output DACs
- Output reference power
Interesting stuff:
- If the clock coming from the FPGA won't live up to our expectations during testing, we can use another source and hang it on the connectors marked by 11.
- The clock from the FGPA is slightly set apart from the bigger data connection, because the harmonics from that 40 MHz signal have a higher chance of interfering with the data lines. Note that at a later time, we'll have a 1 Hz synchronization pulse coming in from outside. This is because our electronics are only part of the whole system and there must be a system-wide clock as well. Otherwise our clocks would deviate as time progresses (think days here).
- There's another clock coming in at 1.25 MHz for the housekeeping ADCs, on the wide ribbon.
- The input marked with 9 is there to test the stability of the DACs. We can feed in funny signals and this shouldn't influence the output of the DACs, marked with 14.